1. Technical Field
The present invention relates to a semiconductor memory apparatus, more particularly, to a semiconductor memory apparatus and a read/write control method thereof.
2. Related Art
A conventional semiconductor memory apparatus generates a column address strobe signal CASP in response to a write command or read command, and generates a write control signal WT_EN and a read control signal IO_STROBE using the column address strobe signal CASP.
At this time, the write control signal WT_EN is used to designate the timing of writing external data into the semiconductor memory apparatus, and the read control signal IO_STROBE is used to designate the timing of reading out data stored in the semiconductor memory apparatus.
The operation of generating the write control signal WT_EN and the read control signal IO_STROBE will be described with reference to FIG. 1 when CMD to CMD delay (tCCD), an operation standard of a semiconductor memory apparatus, that is, delay between two commands CMD, is 2tCK.
According to a write command WTi and a read command RDi, positive-triggering pulses of column address strobe signal CASP having a width of 1tCK are sequentially generated.
According to the sequentially-generated pulses of column address strobe signal CASP, an internal signal PRE_AYP having a pulse width of 2tCK is generated.
At this time, the internal signal PRE_AYP should be generated in the form of two independent pulses for the write command WTi and the read command RDi, respectively.
However, since the CMD to CMD delay (tCCD) is 2tCK and the pulse width of the internal signal PRE_AYP is also 2tCK, the margin between the pulses of the internal signal PRE_AYP has a negative value. Accordingly, the internal signal PRE_AYP is generated in the form of one pulse in which two pulses become one.
As a result, an internal signal AYP which should be generated in the form of two independent pulses is also generated in the form of one pulse.
Finally, a write control signal WT_EN and a read control signal IO_STROBE, which abnormally have the same activation timing, are generated.
FIG. 2 is a timing diagram showing a case in which the internal signal PRE_AYP has a pulse width of less than 2tCK, for example, 1.5tCK.
In this case, the internal signal PRE_AYP and another internal signal AYP are respectively generated in the form of two independent pulses.
Accordingly, the write control signal WT_EN and the read control signal IO_STROBE are generated with a slight time difference provided therebetween.
However, since the timing margin for the internal signal AYP to latch an address ADD, that is, the sum of setup margin and hold margin becomes 2tCK less the AYP pulse width, the setup margin and the hold margin become insufficient. Furthermore, when a signal delay value or phase variation occurs due to a PVT variation, the write control signal WT_EN and the read control signal IO_STROBE may not be generated at accurate timings.